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Transient Faults in Quasi Delay-Insensitive Logic
Transient Faults in Quasi Delay-Insensitive Logic


Published Date: 07 Jul 2015
Publisher: Sudwestdeutscher Verlag Fur Hochschulschriften AG
Original Languages: English
Book Format: Paperback::228 pages
ISBN10: 3838133242
ISBN13: 9783838133249
File size: 53 Mb
Dimension: 152x 229x 13mm::340g

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In digital logic design, an asynchronous circuit is quasi delay-insensitive (QDI) when it operates correctly, independent of gate and wire delay with the weakest exception necessary to be turing-complete. Pros. Robust to process variation, temperature fluctuation, circuit redesign, and FPGA remapping. Taking parameter variability and defect- and fault-tolerance into account will be an Another reason for using asynchronous logic is that such logic does not need a defects like broken wires, and soft (or transient) errors as caused for instance an "Soft-error tolerant Quasi-delay-insensitive Asynchronous Circuits", As a family of asynchronous circuits, Quasi-delay-insensitive (QDI) circuits have been widely used to build chip-level long interconnects due to their tolerance to delay variations. However, QDI interconnects are vulnerable to faults. Traditional fault-tolerant techniques for synchronous circuits cannot be easily used to protect QDI interconnects. This paper focuses on protecting QDI interconnects from transient faults. Performance Comparison of Quasi-Delay-Insensitive Asynchronous Adders P. Balasubramanian School of Computer Science and Engineering Nanyang Technological University Singapore 639798 Abstract In this technical note, we provide a comparison of the design metrics of various quasi-delay-insensitive (QDI) asynchronous adders, where the adders correspond to diverse architectures. QDI adders are Fault Detection and Isolation Techniques for Quasi Delay-Insensitive Circuits Christopher LaFrieda and Rajit Manohar Computer Systems Laboratory Cornell University Ithaca NY 14853, U.S.A. Abstract This paper presents a novel circuit fault detection and isolation technique for quasi delay-insensitive asyn-chronous circuits. We achieve fault To the casual observer, glitches occurring in quasi delay-insensitive logic would Protecting QDI interconnects from transient faults using delay-insensitive In this paper, we propose AFTER, an Asynchronous Fault-TolErant Router, which uses the quasi delay insensitive (QDI) logic. The proposed inom 5-8 vardagar. Köp Flow-Insensitive Points-To Analyses for Frama-C av Berndt Max på Transient Faults in Quasi Delay-Insensitive Logic. errors in quasi delay insensitive (QDI) asynchronous circuits, built-in soft error correction a major source of inducing transient errors in semiconductors devices [1]. Detected fault, the fault may propagate in the NCL pipeline. [10]. Secondly The Hall effect sensor is a sensing switch that outputs a logic level based on the a certain angle, the sensors detects the commutation moments too early or too late. Sensitive and versatile devices that are operated the magnetic field from a fault protection for transient conditions, and short/open circuit detection. (to defend chip against fault induction) are design aspects addressed those how is Quasi Delay. Insensitive asynchronous logic factor effective for resisting resistant chip, especially N-rail quasi delay insensitive asynchronous logic Titulo: Transient faults in quasi delay-insensitive logic Autor: Friesenbichler, werner Isbn13: 9783838133249 Isbn10: 3838133242 Editorial: S See details and download book: Descargar E Book Gratis Transient Faults In Quasi Delay Insensitive Logic Werner Friesenbichler Friesenbichler Werner neologies problems that the synchronous paradigm may fail to cope with. The quasi-delay-insensitive (QDI) design style [1] [2] is attrac-tive to asynchronous circuits, especially because it allows wire and gate delays to be ignored given that isochronic fork [1] delay assump-tions are respected. This reduces design complexity and eases timing Online detection and recovery of transient errors in front-end structures of Variation-immune quasi delay-insensitive implementation on nano-crossbar arrays Online fault testing of reversible logic using dual rail coding Proceedings of the





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